As dimensions of semiconductor devices continue to shrink, alignment of individual device components, and compensation for misalignment become increasingly important. Problems associated with feature misalignment can cause shorting and other catastrophic device failure.
In forming semiconductor devices, it is not uncommon to use a conductive projection of material such as a conductive plug to form an intermediate electrical connection between a substrate node location and a device component. An exemplary conductive projection is shown in FIGS. 1-3.
Referring to FIG. 1, a semiconductor wafer fragment is shown generally at 20 and comprises a semiconductive substrate 22. In the context of this document, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
A pair of isolation oxide regions 24 are formed over substrate 22. A plurality of conductive lines 26 are provided and typically include a polysilicon layer 28, a silicide layer 30 and an insulative cap 32. Sidewall spacers 34 are provided over conductive and non-conductive portions of line 26. Diffusion regions 35 are provided and constitute node locations with which electrical communication is desired. Wafer fragment 20 comprises a portion of a dynamic random access memory (DRAM) device. Conductive projections 36 are provided. A centermost of the conductive projections 36 is positioned to establish electrical communication between diffused regions and a bit line yet to be formed. The conductive projections are typically formed within an opening in an insulative oxide layer such as borophosphosilicate glass (BPSG), and subsequently planarized. A layer 38 is formed over substrate 22 and comprises an insulative material such as BPSG.
Referring to FIG. 2, a pair of contact openings 40 are formed through layer 38 and outwardly expose the illustrated projections 36. Contact openings 40 constitute openings within which storage capacitors are to be formed. Such capacitors are typically formed by providing a layer of conductive material within opening 40 and over layer 38, and subsequently depositing a capacitor dielectric layer and cell plate layer thereover.
Referring to FIG. 3, an enlarged portion of FIG. 2 shows an example alignment tolerance X between centermost conductive projection 36 and a dashed extension of the right edge of one opening 40. A misalignment of the mask used to form contact opening 40 which is greater than X, and in the direction of the conductive projection, can result in overlap of contact opening 40 and centermost conductive projection 36. Such would subsequently cause conductive capacitor material provided into contact opening 40 to be shorted with centermost conductive projection 36 thereby rendering this portion of the device inoperative.
This invention arose out of concerns associated with increasing alignment tolerances between conductive projections and electrical components formed over a semiconductor wafer. The artisan will appreciate other applicability, with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the doctrine of equivalents.